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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3028F 数据表(PDF) 312 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 312 Page - Renesas Technology Corp |
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312 / 923 page  Rev. 2.00, 09/03, page 282 of 890 Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin logic level is read. Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 P9 0 R/W 4 P9 0 R/W 4 3 P9 0 R/W 3 2 P9 0 R/W 2 1 P9 0 R/W 1 0 P9 0 R/W 0 Reserved bits Port 9 data 5 to 0 These bits store data for port 9 pins 5 P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. |
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