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SPC560P60L3 数据表(PDF) 7 Page - STMicroelectronics |
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SPC560P60L3 数据表(HTML) 7 Page - STMicroelectronics |
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7 / 104 page ![]() SPC56xP54x, SPC56xP60x Introduction Doc ID 18340 Rev 3 7/104 1 Introduction 1.1 Document overview This document provides electrical specifications, pin assignments, and package diagrams for the SPC56xP54/60 series of microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical characteristics. For functional characteristics, refer to the device reference manual. 1.2 Description This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis applications specifically the airbag application. This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category. It operates up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 1.3 Device comparison Table 2 provides a summary of different members of the SPC56xP54/60 family and their features—relative to Full-featured version—to enable a comparison among the family members and an understanding of the range of functionality offered within this family. Table 2. SPC56xP54/60 device comparison Feature SPC560P54 SPC560P60 SPC56AP54 SPC56AP60 Code Flash memory (with ECC) 768 KB 1 MB 768 KB 1 MB Data Flash / EE (with ECC) 64 KB SRAM (with ECC) 64 KB 80 KB 64 KB 80 KB Processor core 32-bit e200z0h 32-bit Dual e200z0h Instruction set VLE CPU performance 0-64 MHz FMPLL (frequency-modulated phase- locked loop) modules 1 INTC (interrupt controller) channels 148 PIT (periodic interrupt timer) 1 (includes four 32-bit timers) |
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