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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SPC560P60L3 数据表(PDF) 91 Page - STMicroelectronics |
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SPC560P60L3 数据表(HTML) 91 Page - STMicroelectronics |
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91 / 104 page  SPC56xP54x, SPC56xP60x Electrical characteristics Doc ID 18340 Rev 3 91/104 Figure 28. External interrupt timing 3.18.5 DSPI timing IRQ 2 3 1 Table 41. DSPI timing(1) No. Symbol C Parameter Conditions Min Max Unit 1tSCK CC D DSPI cycle time Master (MTFE = 0) 60 — ns Slave (MTFE = 0) 60 — 2tCSC CC D PCS to SCK delay — 16 — ns 3tASC CC D After SCK delay — 26 — ns 4tSDC CC D SCK duty cycle — 0.4 × tSCK 0.6 × tSCK ns 5tA CC D Slave access time SS active to SOUT valid — 30 ns 6tDIS CC D Slave SOUT disable time SS inactive to SOUT High-Z or invalid — 16 ns 7tPCSC CC D PCSx to PCSS time — 13 — ns 8tPASC CCDPCSS to PCSx time — 13 — ns 9tSUI CC D Data setup time for inputs Master (MTFE = 0) 35 — ns Slave 4— Master (MTFE = 1, CPHA = 0) 35 — Master (MTFE = 1, CPHA = 1) 35 — 10 tHI CC D Data hold time for inputs Master (MTFE = 0) –5 — ns Slave 4 — Master (MTFE = 1, CPHA = 0) 11 — Master (MTFE = 1, CPHA = 1) –5 — 11 tSUO CC D Data valid (after SCK edge) Master (MTFE = 0) — 12 ns Slave — 36 Master (MTFE = 1, CPHA = 0) — 12 Master (MTFE = 1, CPHA = 1) — 12 |
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