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SPC560P60L3 数据表(PDF) 83 Page - STMicroelectronics |
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SPC560P60L3 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 104 page ![]() SPC56xP54x, SPC56xP60x Electrical characteristics Doc ID 18340 Rev 3 83/104 3.17 AC specifications 3.17.1 Pad AC specifications 3.18 AC timing characteristics 3.18.1 RESET pin characteristics The SPC56xP54/60 implements a dedicated bidirectional RESET pin. Table 36. Output pin transition times Symbol C Parameter Conditions(1) Value Unit Min Typ Max Ttr CC D Output transition time output pin(2) SLOW configuration CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 —— 50 ns TCL = 50 pF — — 100 DCL = 100 pF — — 125 DCL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 40 TCL = 50 pF — — 50 DCL = 100 pF — — 75 Ttr CC D Output transition time output pin(2) MEDIUM configuration CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 —— 10 ns TCL = 50 pF — — 20 DCL = 100 pF — — 40 DCL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 —— 12 TCL = 50 pF — — 25 DCL = 100 pF — — 40 Ttr CC D Output transition time output pin(2) FAST configuration CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 —— 4 ns CL = 50 pF — — 6 CL = 100 pF — — 12 CL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 —— 4 CL = 50 pF — — 7 CL = 100 pF — — 12 Tsim (3) CC T Symmetric, same drive strength between N and P transistor VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 4 ns VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 5 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified 2. CL includes device and package capacitances (CPKG < 5 pF). 3. Transition timing of both positive and negative slopes will differ maximum 50% |
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