SPC560P60L3 datasheet(25/104 Pages) STMICROELECTRONICS

25 / 104 page

SPC56xP54x, SPC56xP60x

Introduction

Doc ID 18340 Rev 3

25/104

The Nexus Interface provides the following features:

●

Configured via the IEEE 1149.1

●

All Nexus port pins operate at VDDIO (no dedicated power supply)

●

Nexus 2+ features supported

–

Static debug

–

Watchpoint messaging

–

Ownership trace messaging

–

Program trace messaging

–

Real time read/write of any internally memory mapped resources through JTAG

pins

–

Overrun control, which selects whether to stall before Nexus overruns or keep

executing and allow overwrite of information

–

Watchpoint triggering, watchpoint triggers program tracing

–DDR

●

Auxiliary Output Port

–

4 MDO (Message Data Out) pins

–

MCKO (Message Clock Out) pin

–

2 MSEO (Message Start/End Out) pins

–EVTO (Event Out) pin

●

Auxiliary Input Port

–EVTI (Event In) pin

1.5.28

IEEE 1149.1 (JTAG) controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and

connectivity while remaining transparent to system logic when not in test mode. All data

input to and output from the JTAGC block is communicated in serial format. The JTAGC

block is compliant with the IEEE standard.

The JTAG controller provides the following features:

●

IEEE Test Access Port (TAP) interface with four pins (TDI, TMS, TCK, TDO)

●

Selectable modes of operation include JTAGC/debug or normal system operation.

●

A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

–

BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD

●

A 5-bit instruction register that supports the additional following public instructions:

–

ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_CORE0,

ACCESS_AUX_TAP_CORE1, ACCESS_AUX_TAP_NASPS_0,

ACCESS_AUX_TAP_NASPS_1

●

Three test data registers: a bypass register, a boundary scan register, and a device

identification register.

●

A TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry.

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