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SPC560P60L3 数据表(PDF) 16 Page - STMicroelectronics |
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SPC560P60L3 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 104 page ![]() Introduction SPC56xP54x, SPC56xP60x 16/104 Doc ID 18340 Rev 3 allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. The INTC provides the following features: ● Unique 9-bit vector for each separate interrupt source ● 8 software triggerable interrupt sources ● 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source ● Ability to modify the ISR or task priority. – Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources. ● 2 external high priority interrupts directly accessing the main core and IOP critical interrupt mechanism The INTC module is replicated for each processor. 1.5.7 System clocks and clock generation The following list summarizes the system clock and clock generation on the SPC56xP54/60: ● Lock detect circuitry continuously monitors lock status ● Loss of clock (LOC) detection for PLL outputs ● Programmable output clock divider ( 1, 2, 4, 8) ● Programmable output clock divider ( 1, 2, 3 to 256) ● eTimer module running at the same frequency as the e200z0h core ● On-chip oscillator with automatic level control ● Internal 16 MHz RC oscillator for rapid start-up and safe mode – Supports frequency trimming by user application 1.5.8 Frequency modulated phase-locked loop (FMPLL) The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio are all software configurable. |
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