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SPC560P60L3 数据表(PDF) 73 Page - STMicroelectronics |
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SPC560P60L3 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 104 page  SPC56xP54x, SPC56xP60x Electrical characteristics Doc ID 18340 Rev 3 73/104 3.13 FMPLL electrical characteristics Table 29. Input clock characteristics Symbol Parameter Min Typ Max Unit fOSC SR Oscillator frequency 4 — 40 MHz fCLK SR Frequency in bypass — — 64 MHz trCLK SR Rise/fall time in bypass — — 1 ns tDC SR Duty cycle 47.5 50 52.5 % Table 30. PLLMRFM electrical specifications (VDDPLL = 1.08 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH) Symbol Parameter Conditions Value Unit min max fref_crystal fref_ext D PLL reference frequency range(1) Crystal reference 4 40 MHz fpll_in D Phase detector input frequency range (after pre-divider) —4 16 MHz fFMPLLOUT D Clock frequency range in normal mode — 4 120 MHz fFREE P Free running frequency Measured using clock division — typically /16 20 150 MHz fsys D On-chip PLL frequency — 16 64 MHz tCYC D System clock period — — 1 / fsys ns fLORL fLORH D Loss of reference frequency window(2) Lower limit 1.6 3.7 MHz Upper limit 24 56 fSCM D Self-clocked mode frequency(3),(4) —20 150 MHz CJITTER T CLKOUT period jitter(5),(6),(7),(8) Short-term jitter(9) fSYS maximum –4 4 % fCLKOUT Long-term jitter (avg. over 2 ms interval) fPLLIN = 16 MHz (resonator) , fPLLCLK at 64 MHz, 4000 cycles —10 ns tlpll DPLL lock time (10), (11) —— 200 µs tdc D Duty cycle of reference —40 60 % fLCK D Frequency LOCK range — –6 6 % fsys fUL D Frequency un-LOCK range — –18 18 % fsys fCS fDS D Modulation Depth Center spread ±0.25 ±4.0(12) %fsys Down Spread –0.5 –8.0 fMOD D Modulation frequency(13) —— 70 kHz 1. Considering operation with PLL not bypassed. |
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