SPC560P60L3 datasheet(15/104 Pages) STMICROELECTRONICS

15 / 104 page

SPC56xP54x, SPC56xP60x

Introduction

Doc ID 18340 Rev 3

15/104

The flash memory module provides the following features:

●

Up to 1024 KB flash memory

–

14 blocks (2×16 KB + 2×32 KB + 2×16 KB + 2×64 KB + 6×128 KB) code flash

–

4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash

–

Full Read While Write (RWW) capability between code and data flash

●

Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch

buffers can be configured to prefetch code or data or both)

●

Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page

buffer miss at 64 MHz

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Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

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Hardware and software configurable read and write access protections on a per-master

basis.

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Configurable access timing allowing use in a wide range of system frequencies.

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Multiple-mapping support and mapping-based block access timing (0–31 additional

cycles) allowing use for emulation of other memory types.

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Software programmable block program/erase restriction control.

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Erase of selected block(s)

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Read page size of 128 bits (4 words)

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64-bit ECC with single-bit correction, double-bit detection for data integrity

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Embedded hardware program and erase algorithm

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Erase suspend, program suspend and erase-suspended program

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Censorship protection scheme to prevent flash memory content visibility

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Hardware support for EEPROM emulation

1.5.5

On-chip SRAM with ECC

The SPC56xP54/60 SRAM module provides a general-purpose memory of up to 80 KB.

The SRAM module provides the following features:

●

Supports read/write accesses mapped to the SRAM memory from any master

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Up to 80 KB general purpose RAM

–

2 blocks (48 KB + 32 KB)

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Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of

memory

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Typical SRAM access time: 0 wait state for reads and 32-bit writes; 1 wait state for 8-

and 16-bit writes if back to back with a read to same memory block

1.5.6

Interrupt controller (INTC)

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt

requests, suitable for statically scheduled hard real-time systems.

For high priority interrupt requests, the time from the assertion of the interrupt request from

the peripheral to when the processor is executing the interrupt service routine (ISR) has

been minimized. The INTC provides a unique vector for each interrupt request source for

quick determination of which ISR needs to be executed. It also provides an ample number of

priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To

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