SPC560P60L3 datasheet(17/104 Pages) STMICROELECTRONICS

17 / 104 page

SPC56xP54x, SPC56xP60x

Introduction

Doc ID 18340 Rev 3

17/104

The FMPLL has the following major features:

●

Input clock frequency from 4 MHz to 40 MHz

●

Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

●

Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

●

Modulation enabled/disabled through software

●

Triangle wave modulation

●

Programmable modulation depth (±0.25% to ±4% deviation from center frequency)

–

Programmable modulation frequency dependent on reference frequency

●

Self-clocked mode (SCM) operation

1.5.9

Main oscillator

The main oscillator provides these features:

●

Input frequency range 4 MHz to 40 MHz

●

Crystal input mode or Oscillator input mode

●

PLL reference

1.5.10

Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current

charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap

reference voltage.

The RC Oscillator provides these features:

●

Nominal frequency 16 MHz

●

±6% variation over voltage and temperature after process trim

●

Clock output of the RC oscillator serves as system clock source in case loss of lock or

loss of clock is detected by the PLL

●

RC oscillator is used as the default system clock during startup

1.5.11

Periodic interrupt timer (PIT)

The PIT module implements these features:

●

Up to four general purpose interrupt timers

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32-bit counter resolution

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Clocked by system clock frequency

●

Each channel can be used as trigger for a DMA request

1.5.12

System timer module (STM)

The STM module implements these features:

●

32-bit up counter with 8-bit prescaler

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Four 32-bit compare channels

●

Independent interrupt source for each channel

●

Counter can be stopped in debug mode

The STM module is replicated for each processor.

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