SPC560P60L3 datasheet(76/104 Pages) STMICROELECTRONICS

76 / 104 page

Electrical characteristics

SPC56xP54x, SPC56xP60x

76/104

Doc ID 18340 Rev 3

The filter at the input pins must be designed taking into account the dynamic characteristics

of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the

sampling capacitance: being CS and CP2 substantially two switched capacitances, with a

frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground.

For instance, assuming a conversion rate of 1 MHz, with CS + CP2 equal to 3 pF, a

resistance of 330 k

 is obtained (R

EQ = 1 / (fc × (CS + CP2)), where fc represents the

conversion rate at the considered channel). To minimize the error induced by the voltage

partitioning between this resistance (sampled voltage on CS + CP2) and the sum of RS + RF

, the external circuit must be designed to respect the Equation 4:

Equation 4

Equation 4 generates a constraint for external network design, in particular on resistive

path. Internal switch resistances (RSW and RAD) can be neglected with respect to external

resistances.

Figure 16. Input equivalent circuit (precise channels)

---------------------



--- LSB



RSW1

CP2

VDD

Sampling

Source

Filter

Current Limiter

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

RSW1 Channel Selection Switch Impedance

RAD Sampling Switch Impedance

Pin Capacitance (two contributions, CP1 and CP2)

Sampling Capacitance

CP1

RAD

Channel

Selection

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