SPC560P60L3 datasheet(85/104 Pages) STMICROELECTRONICS

85 / 104 page

SPC56xP54x, SPC56xP60x

Electrical characteristics

Doc ID 18340 Rev 3

85/104

Table 37.

RESET electrical characteristics

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

VIH

SR P

Input High Level CMOS

(Schmitt Trigger)

—

0.65VDD —VDD+0.4

VIL

SR P

Input low Level CMOS

(Schmitt Trigger)

—

0.4

—

0.35VDD

VHYS

CC C

Input hysteresis CMOS

(Schmitt Trigger)

—0.1VDD

——

VOL

CC P Output low level

Push Pull, IOL = 2mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

—

0.1VDD

Push Pull, IOL = 1mA,

VDD = 5.0 V ± 10%, PAD3V5V = 1

(2)

—

0.1VDD

Push Pull, IOL = 1mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

——

0.5

Ttr

CC D

Output transition time

output pin(3)

MEDIUM configuration

CL = 25pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——10

CL = 50pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——20

CL = 100pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——40

CL = 25pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——12

CL = 50pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——25

CL = 100pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——40

WFRST SR P RESET input filtered pulse

—

WNFRST SR P

RESET input not filtered

pulse

—500

—

TPOR

CC D

maximum delay before

internal reset is released

after all VDD_HV reach

nominal supply

Monotonic VDD_HV supply ramp

—

|IWPU|CC P

Weak pull-up current

absolute value

VDD = 3.3 V ± 10%, PAD3V5V = 1

—

150

µA

VDD = 5.0 V ± 10%, PAD3V5V = 0

—

150

VDD = 5.0 V ± 10%, PAD3V5V = 1

(4)

—

250

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified

This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device

reference manual).

CL includes device and package capacitance (CPKG <5 pF).

The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

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