SPC560P60L3 datasheet(81/104 Pages) STMICROELECTRONICS

81 / 104 page

SPC56xP54x, SPC56xP60x

Electrical characteristics

Doc ID 18340 Rev 3

81/104

3.16

Flash memory electrical characteristics

TUE

Total unadjusted error with

current injection

16 precision channels

–3

—

LSB

TUE

Total unadjusted error with

current injection

10 standard channels

–4

—

LSB

VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to TA MAX, unless otherwise specified and analog input voltage from

VSS_HV_AD to VDD_HV_AD.

2. VINAN may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.

During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the

sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock tADC_S depend on programming.

This parameter includes the sample time tADC_S.

20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.

See Figure 16.

Table 32.

ADC conversion characteristics (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

Table 33.

Program and erase specifications

Symbol

Parameter

Conditions

Value

Unit

Min Typ(1)

Initial

max(2)

Max(3)

Twprogram

P Word Program (32 bits) Time(4)

Data Flash

—

500

µs

Tdwprogram

P Double Word (64 bits) Program Time(4)

Code Flash

—

500

µs

TBKPRG

P Bank Program (64 KB)(4), (5)

Data Flash

—

0.49

1.2

4.1

P Bank Program (1056 KB)(4), (5)

Code Flash

—

2.6

6.6

TMDPRG

P Module Program (512 KB)(4)

Code Flash

—

1.3

1.65

T16kpperase P 16 KB Block Pre-program and Erase Time

Code Flash

—

200

500

5000

Data Flash

700

800

T32kpperase P 32 KB Block Pre-program and Erase Time

Code Flash

—

300

600

5000

T64kpperase P 64 KB Block Pre-program and Erase Time

Code Flash

—

400

900

5000

T128kpperase P 128 KB Block Pre-program and Erase Time

Code Flash

—

600

1300

5000

tESRT

P Erase Suspend Request Rate(6)

Code Flash

——

—

Data Flash

Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change

pending device characterization.

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

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