SPC560P60L3 datasheet(103/104 Pages) STMICROELECTRONICS

103 / 104 page

SPC56xP54x, SPC56xP60x

Revision history

Doc ID 18340 Rev 3

103/104

15-May-2012

Removed “Enhanced Full-featured” version.

In the cover page, added “(1 × Master/Slave, 1 × Master Only)“ at the

end of the bullet “2 LINFlex modules (LIN 2.1)”

Table 2: SPC56xP54/60 device comparison, updated the value of

“LINFLEX module” to “2 (1 × Master/Slave, 1 × Master only)”

Section 1.5.4: On-chip flash memory with ECC

replaced two occurrences of “3 wait states” to “2 wait states”

replaced 60 MHz to 64 MHz

Section 1.5.21: Serial communication interface module (LINFlex),

updated first bullet to “Supports LIN Master mode (on both modules),

LIN Slave mode (on one module) and UART mode”

Section 1.5.24: Analog-to-digital converter (ADC), removed bullet

concerning the analog watchdogs from Normal mode features.

Table 5: Supply pins, removed VREG_BYPASS row.

Table 6: System pins:

added VREG_BYPASS row

added a footnote about RESET

Table 9: Absolute maximum ratings:

changed typical value of TVDD to 0.25 and added a footnote

added VINAN entry

Updated Section 3.8.1: Voltage regulator electrical characteristics

Updated Table 14: EMI testing specifications

Table 18: Low voltage monitor electrical characteristics, changed

maximum value of VMLVDDOK_H to 1.15

Table 20: DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0),

added IPU and IPD rows for RESET pin.

Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0):

added maximum values of IDD_LV_CORE for: RUN, HALT, and STOP

mode

updated values and parameter classification of IDD_FLASH

Table 22: DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1),

added IPU and IPD rows for RESET pin.

Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1):

added maximum values of IDD_LV_CORE for: RUN, HALT, and STOP

mode

updated values and parameter classification of IDD_FLASH

Added Table 26: I/O consumption

Table 31: 16 MHz RC oscillator electrical characteristics, changed

minimum and maximum values of



RCMVAR respectively to -6 and 6.

Renamed Figure 16: Input equivalent circuit (precise channels) (was

“Input equivalent circuit”)

Added Figure 17: Input equivalent circuit (extended channels)

Section 3.15.1: Input impedance and ADC accuracy, updated

Equation 4 and Equation 10

Table 32: ADC conversion characteristics, added VINAN, CP3 and RSW2

rows

Table 44.

Document revision history (continued)

Date

Revision

Substantive changes

SPC560P60L3 数据表(PDF) 103 Page - STMicroelectronics

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