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WM8904ECS/R 数据表(PDF) 63 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 63 Page - Wolfson Microelectronics plc |
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63 / 188 page  Pre-Production WM8904 w PP, Rev 3.3, September 2012 63 The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is used for the left and right digital audio interface data. These register bits are described in Table 27. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (18h) Audio Interface 0 7 AIFADCL_SRC 0 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 6 AIFADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel R38 (26h) ADC Digital 0 1 ADCL_DATINV 0 Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted 0 ADCR_DATINV 0 Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted Table 27 ADC Routing and Control The input data source for each DAC can be changed under software control using register bits AIFDACL_SRC and AIFDACR_SRC. The polarity of each DAC input may also be modified using register bits DACL_DATINV and DACR_DATINV. These register bits are described in Table 28. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (18h) Audio Interface 0 12 DACL_DATINV 0 Left DAC Invert 0 = Left DAC output not inverted 1 = Left DAC output inverted 11 DACR_DATINV 0 Right DAC Invert 0 = Right DAC output not inverted 1 = Right DAC output inverted 5 AIFDACL_SRC 0 Left DAC Data Source Select 0 = Left DAC outputs left interface data 1 = Left DAC outputs right interface data 4 AIFDACR_SRC 1 Right DAC Data Source Select 0 = Right DAC outputs left interface data 1 = Right DAC outputs right interface data Table 28 DAC Routing and Control |
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