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WM8904ECS/R 数据表(PDF) 74 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 74 Page - Wolfson Microelectronics plc |
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74 / 188 page  WM8904 Pre-Production w PP, Rev 3.3, September 2012 74 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 4 HPL_ENA 0 Enables HPL input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the first step of the HPL Enable sequence. 3 HPR_RMV_SHO RT 0 Removes HPR short 0 = HPR short enabled 1 = HPR short removed For normal operation, this bit should be set as the final step of the HPR Enable sequence. 2 HPR_ENA_OUTP 0 Enables HPR output stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled. 1 HPR_ENA_DLY 0 Enables HPR intermediate stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPR_ENA. 0 HPR_ENA 0 Enables HPR input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the first step of the HPR Enable sequence. |
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