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数据搜索系统，热门电子元器件搜索 |
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WM8904ECS/R 数据表(PDF) 91 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 91 Page - Wolfson Microelectronics plc |
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91 / 188 page  Pre-Production WM8904 w PP, Rev 3.3, September 2012 91 MASTER AND SLAVE MODE OPERATION The WM8904 digital audio interface can operate in master or slave mode, as shown in Figure 40 and Figure 41. Figure 40 Master Mode Figure 41 Slave Mode In master mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV. In master mode, LRCLK is derived from BCLK via a programmable division set by LRCLK_RATE. The BCLK input to this divider may be internal or external, allowing mixed master and slave modes. The direction of these signals and the clock frequencies are controlled as described in the “Digital Audio Interface Control” section. BCLK and LRCLK can be enabled as outputs in Slave mode, allowing mixed Master/Slave operation - see “Digital Audio Interface Control”. OPERATION WITH TDM Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same bus. The WM8904 ADCs and DACs support TDM in master and slave modes for all data formats and word lengths. TDM is enabled and configured using register bits defined in the “Digital Audio Interface Control” section. WM8904 Processor WM8904 or Similar CODEC ADCDAT LRCLK DACDAT BCLK ADCDAT LRCLK DACDAT BCLK WM8904 Processor WM8904 or Similar CODEC ADCDAT LRCLK DACDAT BCLK ADCDAT LRCLK DACDAT BCLK Figure 42 TDM with WM8904 as Master Figure 43 TDM with Other CODEC as Master |
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