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WM8904ECS/R 数据表(PDF) 97 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 97 Page - Wolfson Microelectronics plc |
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97 / 188 page  Pre-Production WM8904 w PP, Rev 3.3, September 2012 97 DIGITAL AUDIO INTERFACE CONTROL The register bits controlling audio data format, word length, left/right channel data source and TDM are summarised in Table 54. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (18h) Audio Interface 0 7 AIFADCL_SR C 0 Left Digital Audio channel source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 6 AIFADCR_SR C 1 Right Digital Audio channel source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 5 AIFDACL_SR C 0 Left DAC Data Source Select 0 = Left DAC outputs left channel data 1 = Left DAC outputs right channel data 4 AIFDACR_SR C 1 Right DAC Data Source Select 0 = Right DAC outputs left channel data 1 = Right DAC outputs right channel data R25 (19h) Audio Interface 1 13 AIFDAC_TDM 0 DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT 12 AIFDAC_TDM _CHAN 0 DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 11 AIFADC_TDM 0 ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT 10 AIFADC_TDM _CHAN 0 ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 7 AIF_BCLK_IN V 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 4 AIF_LRCLK_I NV 0 LRC Polarity / DSP Mode A-B select. Right, left and I2S modes – LRC polarity 0 = Not Inverted 1 = Inverted DSP Mode – Mode A-B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 3:2 AIF_WL [1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 1:0 AIF_FMT [1:0] 10 Digital Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP Table 54 Digital Audio Interface Data Control |
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