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WM8904ECS/R 数据表(PDF) 26 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 26 Page - Wolfson Microelectronics plc |
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26 / 188 page ![]() WM8904 Pre-Production w PP, Rev 3.3, September 2012 26 AUDIO INTERFACE TIMING MASTER MODE BCLK (Output) ADCDAT LRCLK (Output) t DL DACDAT t DDA t DHT t DST Figure 2 Audio Interface Timing – Master Mode Test Conditions DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA = +25 oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode LRCLK propagation delay from BCLK falling edge tDL 20 ns ADCDAT propagation delay from BCLK falling edge tDDA 20 ns DACDAT setup time to BCLK rising edge tDST 20 ns DACDAT hold time from BCLK rising edge tDHT 10 ns |
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