WM8904ECSSLASHR datasheet(92/188 Pages) WOLFSON

92 / 188 page

WM8904

Pre-Production

PP, Rev 3.3, September 2012

WM8904

Processor

WM8904 or

Similar

CODEC

ADCDAT

LRCLK

DACDAT

BCLK

ADCDAT

LRCLK

DACDAT

BCLK

Figure 44 TDM with Processor as Master

Note: The WM8904 is a 24-bit device. If the user operates the WM8904 in 32-bit mode then the 8

LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore

recommended to add a pull-down resistor if necessary to the DACDAT line and the ADCDAT line in

TDM mode.

BCLK FREQUENCY

The BCLK frequency is controlled relative to SYSCLK by the BCLK_DIV divider. Internal clock divide

and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a predictable

and repeatable position relative to each other and relative to the data for a given combination of

DAC/ADC sample rate and BCLK_DIV settings.

BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also the “Clocking and

Sample Rates” section for more information.

AUDIO DATA FORMATS (NORMAL MODE)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 45 Right Justified Audio Interface (assuming n-bit word length)

WM8904ECS/R 数据表(PDF) 92 Page - Wolfson Microelectronics plc