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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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WM8904ECS/R 数据表(PDF) 27 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 27 Page - Wolfson Microelectronics plc |
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27 / 188 page  Pre-Production WM8904 w PP, Rev 3.3, September 2012 27 SLAVE MODE BCLK (input) LRCLK (input) ADCDAT (output) DACDAT (input) tDS tDD tDH tLRH tLRSU tBCH tBCL tBCY Figure 3 Audio Interface Timing – Slave Mode Test Conditions DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA = +25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Slave Mode BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 20 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 20 ns DACDAT set-up time to BCLK rising edge tDS 20 ns Note: BCLK period must always be greater than or equal to MCLK period. |
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