数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

WM8940CGEFL/RV 数据表(PDF) 55 Page - Wolfson Microelectronics plc

部件名 WM8940CGEFL/RV
功能描述  Mono CODEC with Speaker Driver
PDF  91 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8940CGEFL/RV 数据表(HTML) 55 Page - Wolfson Microelectronics plc

Back Button WM8940CGEFL/RV Datasheet HTML 51Page - Wolfson Microelectronics plc WM8940CGEFL/RV Datasheet HTML 52Page - Wolfson Microelectronics plc WM8940CGEFL/RV Datasheet HTML 53Page - Wolfson Microelectronics plc WM8940CGEFL/RV Datasheet HTML 54Page - Wolfson Microelectronics plc WM8940CGEFL/RV Datasheet HTML 55Page - Wolfson Microelectronics plc WM8940CGEFL/RV Datasheet HTML 56Page - Wolfson Microelectronics plc WM8940CGEFL/RV Datasheet HTML 57Page - Wolfson Microelectronics plc WM8940CGEFL/RV Datasheet HTML 58Page - Wolfson Microelectronics plc WM8940CGEFL/RV Datasheet HTML 59Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 55 / 91 page
background image
Production Data
WM8940
w
PD, Rev 4.3, November 2011
55
Figure 29 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1)
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below.
Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK,
and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with
BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at
the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4
Audio interface
control
9
LOUTR
0
LOUTR control
0=normal
1=Input mono channel data output on both
left and right channels
8
BCP
0
BCLK polarity
0=normal
1=inverted
7
FRAMEP
0
Frame clock polarity (for RJ, LJ and I
2S
formats)
0=normal
1=inverted
DSP Mode control
1 = Configures interface so that MSB is
available on 1st BCLK rising edge after
FRAME rising edge
0 = Configures interface so that MSB is
available on 2nd BCLK rising edge after
FRAME rising edge
6:5
WL
10
Word length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits (see note)
4:3
FMT
10
Audio interface Data Format Select:
00=Right Justified
01=Left Justified
10=I
2S format
11= DSP/PCM mode



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com