WM8940CGEFLSLASHRV datasheet(71/91 Pages) WOLFSON

71 / 91 page

Production Data

WM8940

PD, Rev 4.3, November 2011

Notes:

1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).

2. Register bits marked as “Reserved” should not be changed from the default.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

0 (00h)

[15:0] RESET /

CHIP_ID

N/A

Writing to this register will apply a software reset.

Reading from this register will return the device id

Resetting the

Chip /

Control Interface

1 (01h)

15:9

Reserved

VMID_OP_EN

Enables the non-VMID derived bias current generator

without enabling the VMID buffer. This bit must be set

to 1 if output amplifiers are to be enabled before VMID

is active. Once VMID and VMID buffer are enabled this

bit can be left set to 0 or left set to 1.

Power

Management

LVLSHIFT_EN

Enable bit for the level shifters. 1 for normal operation,

0 for standby.

Power

Management

AUXEN

Auxiliary input buffer enable

0 = OFF

1 = ON

Auxiliary Inputs

PLLEN

PLL enable

0=PLL off

1=PLL on

Master Clock and

Phase Locked

Loop (PLL)

MICBEN

Microphone Bias Enable

0 = OFF (high impedance output)

1 = ON

Microphone

Biasing Circuit

BIASEN

Analogue amplifier bias control

0=Disabled

1=Enabled

Power

Management

2:0

DEVICE_REVIS

ION

000

Readback from this register will return the device

revision in this position

Control Interface

BUFIOEN

Enable bit for the VMID buffer. The VMID buffer is

used to maintain a buffered VMID voltage on all

analogue input and output pins. 1. for normal operation

0. for standby (where inputs and outputs settle to

GND).

Enabling the

Outputs

1:0

VMIDSEL

Reference string impedance to VMID pin:

00=off (open circuit)

01=50kΩ

10=250kΩ

11=5kΩ

Power

Management

2 (02h)

15:5

000h

Reserved

BOOSTEN

Input BOOST enable

0 = Boost stage OFF

1 = Boost stage ON

Input Boost

Reserved

INPPGAEN

Input microphone PGA enable

0 = disabled

1 = enabled

Input Signal Path

Reserved

ADCEN

ADC Enable Control

0 = ADC disabled

1 = ADC enabled

Analogue to

Digital Converter

(ADC)

3 (03h)

15:8

00h

Reserved

WM8940CGEFL/RV 数据表(PDF) 71 Page - Wolfson Microelectronics plc

WM8940CGEFL/RV 数据表(HTML) 71 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表下载

链接网址

WM8940CGEFL/RV 数据表(PDF) 71 Page - Wolfson Microelectronics plc

WM8940CGEFL/RV 数据表(HTML) 71 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表 下载

链接网址

数据表下载