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WM8940CGEFL/RV 数据表(PDF) 73 Page - Wolfson Microelectronics plc |
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WM8940CGEFL/RV 数据表(HTML) 73 Page - Wolfson Microelectronics plc |
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73 / 91 page  Production Data WM8940 w PD, Rev 4.3, November 2011 73 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 1 ALRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=ADC data appear in ‘left’ phase of FRAME 1=ADC data appears in ‘right’ phase of FRAME Digital Audio Interfaces 0 0 Reserved 5 (05h) 15:7 0000 Reserved 6 DAC_LOOPBA CK 0 Digital loopback function 0=No DAC loopback 1=Loopback enabled, DAC data input is fed directly into ADC data output. Digital Audio Interfaces 5 WL8 0 8 Bit Word Length for companding 0=Word Length controlled by WL 1=8 bits Digital Audio Interfaces 4:3 DAC_COMP 00 DAC companding 00=off 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 2:1 ADC_COMP 00 ADC companding 00=off 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 0 ADC_LOOPBA CK 0 Digital loopback function 0=No ADC loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Digital Audio Interfaces 6 (06h) 15:9 00h Reserved 8 CLKSEL 1 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Digital Audio Interfaces 7:5 MCLKDIV 010 Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Digital Audio Interfaces 4:2 BCLKDIV 000 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Digital Audio Interfaces 1 0 Reserved |
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