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WM8940CGEFL/RV 数据表(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8940CGEFL/RV 数据表(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 91 page  WM8940 Production Data w PD, Rev 4.3, November 2011 30 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R34 (22h) ALC Control 3 8 ALCMODE 0 Determines the ALC mode of operation: 0 = ALC mode (Normal Operation) 1 = Limiter mode. 7:4 ALCDCY [3:0] 0011 (26ms/6dB) Decay (gain ramp-up) time (ALCMODE ==0) Per step Per 6dB 90% of range 0000 410us 3.38ms 23.6ms 0001 820us 6.56ms 47.2ms 0010 1.64ms 13.1ms 94.5ms … (time doubles with every step) 1010 or higher 420ms 3.36s 24.2s 0011 (5.8ms/6dB) Decay (gain ramp-up) time (ALCMODE ==1) Per step Per 6dB 90% of range 0000 90.8us 726us 5.23ms 0001 182us 1.45ms 10.5ms 0010 363us 2.91ms 20.9ms … (time doubles with every step) 1010 93ms 744ms 5.36s 3:0 ALCATK [3:0] 0010 (3.3ms/6dB) ALC attack (gain ramp-down) time (ALCMODE == 0) Per step Per 6dB 90% of range 0000 104us 832us 6ms 0001 208us 1.66ms 12ms 0010 416us 3.33ms 24ms … (time doubles with every step) 1010 or higher 106ms 852ms 6.13s 0010 (726us/6dB) ALC attack (gain ramp-down) time (ALCMODE == 1) Per step Per 6dB 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363us 2.62ms 0010 90.8us 726us 5.23ms … (time doubles with every step) 1010 or higher 23.2ms 186ms 1.34s R42 (2Ah) ALC Control 4 1 ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled Table 20 ALC Control Registers NOTE: The Input PGA Volume register R45 must be written with the INPPGAMUTE bit R45[6] set to 0 before setting ALCSEL bit R32[8] to 1. When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. |
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