WM8940CGEFLSLASHRV datasheet(66/91 Pages) WOLFSON

66 / 91 page

WM8940

Production Data

PD, Rev 4.3, November 2011

RESETTING THE CHIP

The WM8940 can be reset by performing a write of any value to the software reset register (address

0 hex). This will cause all register values to be reset to their default values. In addition to this there

is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device

is powered up.

POWER SUPPLIES

The WM8940 requires four separate power supplies:

AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and

mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on

overall power consumption (except for power consumed in the headphone). A larger AVDD slightly

improves audio quality.

SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output

drivers. SPKVDD can range from 2.5V to 3.6V. SPKVDD can be tied to AVDD, but it requires

separate layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder

headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than

AVDD, the output signal may be clipped.

DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces.

DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for

DCVDD is DGND, which is shared with DBVDD.

DBVDD can range from 1.71V to 3.6V. DBVDD return path is through DGND.

It is possible to use the same supply voltage for all four supplies. However, digital and analogue

supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of

the analogue signal paths.

RECOMMENDED POWER UP/DOWN SEQUENCE

In order to minimise output pop and click noise, it is recommended that the WM8940/WM8941 device

is powered up and down using one of the following sequences:

Power Up:

Turn on external power supplies. Wait for supply voltages to settle.

Reset internal registers to default state (software reset).

Enable non-VMID derived bias generator (VMID_OP_EN = 1) and level shifters

(LVLSHIFT_EN = 1).

Enable DAC soft mute (DACMU = 1).

Select Clock source to MCLK (CLKSEL = 0) and audio mode (Master or Slave).

Enable Power on Bias Control (POB_CTRL = 1) and VMID soft start (SOFT_START = 1).

Enable speaker outputs (SPKPEN = 1, SPKNEN = 1) and wait for outputs to settle.

Set VMIDSEL[1:0] bits for 50kΩ reference string impedance.

Wait for the VMID supply to settle. *Note 2.

10.

Enable analogue amplifier bias control (BIASEN = 1) and VMID buffer (BUFIOEN = 1).

*Notes 1 and 2.

11.

Disable Power on Bias Control (POB_CTRL = 0) and VMID soft start (SOFT_START = 0).

12.

Enable DAC (DACEN =1) and Speaker Mixer (SPKMIXEN = 1).

13.

Enable output of DAC to speaker mixer (DAC2SPK = 1).

WM8940CGEFL/RV 数据表(PDF) 66 Page - Wolfson Microelectronics plc

WM8940CGEFL/RV 数据表(HTML) 66 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表下载