WM8940CGEFLSLASHRV datasheet(74/91 Pages) WOLFSON

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WM8940

Production Data

PD, Rev 4.3, November 2011

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

Sets the chip to be master over FRAME and BCLK

0=BCLK and FRAME clock are inputs

1=BCLK and FRAME clock are outputs generated by

the WM8940 (MASTER)

Digital Audio

Interfaces

7 (07h)

15:7

00000

Reserved

POB_CTRL

Power on Bias Control

0=normal (current bias based on VMID)

1=Startup (current bias not based on VMID)

POP Minimisation

SOFT_START

VMID Soft Start

0=disabled

1=enabled

POP Minimisation

TOGGLE

Fast VMID Discharge

0=normal

1=enable (used during powerdown)

POP Minimisation

3:1

000

Approximate sample rate (configures the coefficients

for the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Audio Sample

Rates

SLOWCLKEN

Enables the Timeout Clock for zero cross detection.

Zero Cross

Timeout

8 (08h)

15:8

00h

Reserved

MODE_GPIO

Selects MODE as a GPIO pin

0 = MODE is an input. MODE selects 2-wire mode

when low and 3-wire mode when high.

1 = MODE can be an input or output under the control

of the GPIO control register. Interface operates in 3-

wire mode regardless of what happens on the MODE

pin.

Control Interface

Reserved

5:4

OPCLKDIV

PLL Output clock division ratio

00=divide by 1

01=divide by 2

10=divide by 3

11=divide by 4

General Purpose

Input Output

GPIOPOL

GPIO Polarity invert

0=Non inverted

1=Inverted

General Purpose

Input Output

2:0

GPIOSEL

000

CSB/GPIO pin function select:

000=CSB input

001= Jack insert detect

010=Temp ok

011=Amute active

100=PLL clk o/p

101=PLL lock

110=Reserved

111=Reserved

General Purpose

Input Output

9 (09h)

15:2

Reserved

WM8940CGEFL/RV 数据表(PDF) 74 Page - Wolfson Microelectronics plc

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