WM8940CGEFLSLASHRV datasheet(59/91 Pages) WOLFSON

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Production Data

WM8940

PD, Rev 4.3, November 2011

INTEGER N DIVISION

The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12.

If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low

power operation.

INPUT CLOCK

(F1)

DESIRED PLL OUTPUT

(F2)

DIVISION

REQUIRED (R)

FRACTIONAL

DIVISION (K)

INTEGER

DIVISION (N)

SDM

11.2896MHz

90.3168MHz

12.2880MHz

98.3040MHz

Table 48 PLL Modes of Operation (Integer N mode)

FRACTIONAL K MODE

The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up to

1/2

24). If these are used then FRAC_EN must be set. The relationship between the required division

R, the fractional division K[23:0] and the integer division N[3:0] is:

K = 2

24 ( R – N)

where 0 < (R – N) < 1 and K is rounded to the nearest whole number.

EXAMPLE:

PLL input clock (f1) is 12MHz and the required clock (SYSCLK) is 12.288MHz.

R should be chosen to ensure 5 < N < 13. There is a fixed divide by 4 in the PLL and a selectable

divider (MCLKDIV[3:0]) after the PLL which should be set to divide by 2 to meet this requirement.

Enabling the divide by 2 sets the required f2 = 4 * 2 * 12.288MHz = 98.304MHz.

R = 98.304 / 12 = 8.192

N = int R = 8

K = int (2

24 x (8.192 – 8)) = 3221225 = 3126E9h

So N[3:0] will be 8h and K[23:0] will be 3126E9h to produce the desired 98.304MHz clock.

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