WM8940CGEFLSLASHRV datasheet(67/91 Pages) WOLFSON

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Production Data

WM8940

PD, Rev 4.3, November 2011

14.

Disable speaker mute (SPKMUTE = 0) and set SPKVOL = -57dB.

15.

Ramp up the SPKVOL using the following values:

16.

-27 dB, -21 dB, -15 dB, -13 dB, -11 dB, -9 dB, -8 dB, -7 dB, -6 dB, -5 dB, -4 dB, -3 dB, -2

dB, -1 dB, 0 dB.

17.

Disable DAC soft mute (DACMU = 0).

Power Down:

Enable DAC soft mute (DACMU = 1).

Enable non-VMID derived bias generator (VMID_OP_EN = 1).

Enable on Bias Control (POB_CTRL = 1).

Disable analogue amplifier bias control (BIASEN = 0) and VMID (VMIDSEL[1:0] bits set to

OFF).

Enable Fast VMID Discharge (TOGGLE = 1) to discharge VMID capacitor.

Wait for VMID capacitor to fully discharge.

Enable speaker output mute (SPKMUTE = 1).

Disable DAC (DACEN = 0), speaker mixer (SPKMIX = 0), and speaker outputs (SPKPEN =

0 and SPKNEN = 0).

Reset all registers to their default state (software reset).

10.

Turn off external power supply voltages.

Notes:

This step enables the internal device bias buffer and the VMID buffer for unassigned

inputs/outputs. This will provide a startup reference for all inputs and outputs. This will

cause the inputs and outputs to ramp towards VMID in a way that is controlled and

predictable.

Choose the value of VMIDSEL bits based on the startup time (VMIDSEL = 10 for the

slowest startup, VMIDSEL = 11 for the fastest startup). Startup time is defined by the value

of the VMIDSEL bits (the reference impedance) and the external decoupling capacitor on

VMID.

In addition to the power on sequence, it is recommended that the zero cross functions are used when

changing the volume in the PGAs to avoid any audible pops and clicks.

WM8940CGEFL/RV 数据表(PDF) 67 Page - Wolfson Microelectronics plc

WM8940CGEFL/RV 数据表(HTML) 67 Page - Wolfson Microelectronics plc

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