AD6620SSLASHPCB datasheet(36/43 Pages) AD

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AD6620

–36–

REV. 0

SDFE

Serial Data Frame End output. SDFE will go high during the

last SCLK cycle of an active time-slot. The SDFE output of a

master AD6620 can be tied to the input SDFS of an AD6620 in

Serial Cascade Mode in order to provide a hardwired time-slot

scenario. When the Last Bit of SDO data is shifted out of the

Master AD6620, the SDFE signal will be driven high by the

same SCLK rising edge that this bit is clocked out on. On the

falling edge of this SCLK cycle, the Cascaded AD6620 will

sample its SDFS signal, which is hardwired to the SDFE of the

Master. On the very next SCLK edge, A channel: I data of the

Cascaded AD6620 will start shifting out of the port. There will

be no rest between the time-slots of the master and slave.

WL[1:0]

WL defines the Word Length of the serial data stream. The

possible options are 00–6 bit words, 01–24 bit words, 10–32 bit

words and 11–Undefined. This setting controls the width of all

serial words. All words are shifted MSB first and are left justi-

fied, i.e., the first n-bits are valid and any padding that is needed

to fill the word length is added at the end. When the serial word

length is 24 or 32 bits, the I and Q output data is presented with

23-bit resolution.

Table XIV. Setting Serial Word Length

Serial Word Length

WL1

WL0

16-Bit

24-Bit

32-Bit

Disallowed

Append Data signal. In Single Channel Real Mode, when AD is

low the serial data stream consists only of A channel: I and Q

data. If the AD6620 is in Diversity Channel Real Mode, the

serial frame is four words long and consists of both A and B

channel complex data. When the AD signal is high, an extra

serial word is appended to the Serial Frame. This word consists

of any data that is read from the AD6620 internal registers via

the Serial Port. If a Read has not occurred, the data in this word

is zero. The addition of this word allows a Serial System to be

designed so that any AD6620 can have data read at any time

without changing the fixed timing of the serial port.

If the serial transfer includes a register read, the register data is

appended to the serial frame regardless of the state of the AD

pin.

SDIV[3:0]

When the AD6620 is used as a Serial Bus Master the chip gen-

erates a serial clock by dividing down the CLK signal. The

divider ratio is set by the serial division word, SDIV. SDIV is

interpreted as a 4-bit unsigned integer and determines the fre-

quency of the serial clock when the SBM pin is pulled high.

When the AD6620 is in Serial Cascade Mode these bits are

ignored. The following equations express the Serial Clock Fre-

quency as a function of the CLK signal and the SDIV nibble.

SDIV

SCLK

CLK

SCLK

CLK

≠

Serial Port Guidelines

The serial clock, SCLK, must be run at a rate sufficient to clock

all of the serial data out of the port before new data is latched

into the internal I and Q data registers. See the Serial Output

Data Port section for more details. If the serial port is to be used

as a means of programming the part, some extra serial band-

width may also be required to shift data from the internal regis-

ters of the AD6620. When used as a serial bus master SCLK

can run at a maximum rate of half the processing CLK. The

equations below help determine what the minimum serial clock

rate must be in order to insure that data is not lost.

fWL

SCLK

SAMP

TOT

CIC

RCF

×× ×

=×

()

RD = 1 if AD is asserted or if read operations are used from the

serial port; otherwise RD = 0. This term accounts for the band-

width consumed when data is read from the internal control

registers or memory.

JTAG BOUNDARY SCAN

The AD6620 supports a subset of IEEE Standard 1149.1

specifications. For additional details of the standard, please see

“IEEE Standard Test Access Port and Boundary-Scan

Architecture,” IEEE-1149 publication from IEEE.

The AD6620 has five pins associated with the JTAG interface.

These pins are used to access the on-chip Test Access Port

(TAP) and are listed in the table below.

Table XV.

Pin Name

Description

TRST

TAP Reset

TCLK

Test Clock

TMS

TAP Mode Select

TDI

Test Data Input

TDO

Test Data Output

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