AD6620SSLASHPCB datasheet(41/43 Pages) AD

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AD6620

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REV. 0

the outputs. Since the devices are operated in Single Channel

Real mode, this signal will be high for two clock cycles while

two pieces of data are written to the output. The output pairs

consist of I followed by Q. As each chip’s DVOUT cycles high, its

data should be connected to the output bus as shown below.

This effectively forms a MUX that sequentially cycles the out-

put of each of the AD6620s in the system to the output port.

The only remaining issue is retiming the data. Since each AD6620

clocks its data out in two clock cycles, there will be six cycles

where the data is idle. During this period, the last Q out will

remain valid until the next chip in the sequence generates its

DVOUT signal. This normally should pose no problem, but if it

does, the output data could easily go to a FIFO and be retimed

so that output data streams at a regular rate.

DOUT1

CLOCK

DVOUT1

INPUT LATCHING

DOUT1

CLOCK

DVOUT2

INPUT LATCHING

DOUT1

CLOCK

DVOUT3

INPUT LATCHING

DOUT1

CLOCK

DVOUT4

INPUT LATCHING

OUTPUT

LATCHING

Figure 59. Parallel Procession Output Selector

CLOCK

DVOUT1

DVOUT2

DVOUT3

DVOUT4

AD6620–1

AD6620–2

AD6620–3

AD6620–4

SELECTOR

OUTPUT

‘

Figure 60. Timing for Parallel Processing

In the Output Selector above each of the DVOUT lines is ANDed

with main clock. This allows the data out of each of the AD6620s

to be properly latched into the input latches. The DVOUT line is

also responsible for placing the latched outputs on the internal

bus at the proper time. This data is then latched in the output

latch using the internal ORed clocking signals.

The timing for these events is shown in Figure 60. As shown,

the system clock is run at the specified rate. Then the RCF

timing control state machine is responsible for generating the

appropriate sync pulses. When each AD6620 completes its SOP

computation, it generates the DVOUT pulses shown below. Con-

currently, each chip places its IQ data on the output pins of that

device. With this data, the output selector state machine com-

bines all of the data and places the data on the output bus.

Using the AD6620 in a Narrow Band System

A typical interconnection between the AD6600, AD6620 and a

General Purpose DSP. This is an example of an IF sampling

narrow-band system and offers many technical and cost advan-

tages over traditional solutions. In this example, the AD6620 is in

Diversity Channel Real Mode, with the AD6600 sampling a

diversity antenna on its B channel. The AD6620 performs float-

ing-point to fixed-point conversion, digital tuning, digital filter-

ing and decimation of the A/D output data.

MAIN

INPUT

DIVERSITY

INPUT

2 CLK

A/B OUT

3 RSSI BITS

11 DATA BITS

ENCODE

SCLK

SDI

SDO

SDFS

CLK

A/B

E[2...0]

IN[15...5]

AD6620

AD6600

SCLK

SDO

SDI

SDFS

DSP

Figure 61. Implementation of a Narrow Band Receiver

The 2

× CLK on the AD6600 is used as the processing CLK of

the AD6620. The use of this faster clock allows the RCF filter to

process up to twice as many taps per sample. The increased

number of taps available helps to improve the filter characteris-

tics. In some applications an even faster processing clock may be

necessary to allow for improved digital filter performance. In this

case the A/B pin of the AD6620 must be toggled when each

channel input is to be sampled.

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