AD6620SSLASHPCB datasheet(37/43 Pages) AD

37 / 43 page

AD6620

–37–

REV. 0

The AD6620 supports four op codes as shown below. These

instructions set the mode of the JTAG interface.

Table XVI.

Instruction

Op Code

IDCODE

BYPASS

SAMPLE/PRELOAD

EXTEST

The Vendor Identification Code can be accessed through the

IDCODE instruction and has the following format.

Table XVII.

MSB

LSB

Version Part Number

Manufacturing ID #

Mandatory

0000

0010 0111 0111 1110

000 1110 0101

A BSDL file for this device is available from Analog Devices,

Inc. Contact Analog Devices, Inc. for more information.

APPLICATIONS

EVALUATION BOARD

An evaluation board is available for the AD6620. This evalua-

tion board comes complete with an AD6620 and interfaces to a

PC through the printer port. The evaluation board comes com-

plete with software to drive the evaluation board and to design

optimized filters for use with the AD6620. The evaluation board

includes a high speed data interface that mates directly with

evaluation boards for high performance converters such as the

AD6600 and AD6640, allowing digital receivers to be bread-

boarded with only an external RF/IF converter and an interface

to the DSP.

The control software allows access to all of the internal registers

to provide complete programming of the device in a lab setting.

The software can process high speed data as well as digitally

filtered data from the AD6620 allowing analysis of both pre and

post filter channel characteristics. The controlling software can

also be used to spectrally sweep the filter performance, greatly

simplifying verification of any given filter design.

AD6620

LATCH

HI SPEED

DATA

HEADER

LATCH

FIFO

LATCH

TRANSCEIVER

PC PRINTER PORT

LATCH

Figure 52. Evaluation Board Block Diagram

As shown in the block diagram below, the high speed data into

the evaluation board is sent to both the AD6620 and the by-pass

latches. On the output of the AD6620, data is available in either

serial or parallel mode. In serial mode, data may be sent directly

to a DSP for system bread-boarding. In parallel mode, the data

may be sent to the on-board FIFO for spectral analysis by the

included software. For additional information, refer to the

evaluation board manual.

FILTER DESIGN

The AD6620 implements a pair of cascaded CIC filters with a

sum of products FIR filter. The frequency characteristics of the

CIC filters have already been documented. Additional reading

on this class of filters can be found in “An Economical Class of

Digital Filters for Decimation and Interpolation,” by Eugene B.

Hogenauer, IEEE Transactions on Acoustics, Speech, and

Signal Processing, Volume ASSP-29, Number 2, April 1981.

The characteristics of the FIR filter are fully programmable.

The coefficients of this filter may be generated in any number

of ways, using standard procedures such as Parks-McClellan.

Available software from Analog Devices that assists in the design

of filters for this product. This software allows comparison be-

tween different distributions of decimation. The software works

independently of the evaluation board, but easily allows transfer

of design data directly to the evaluation board for immediate

verification of the designed filter.

The normal procedure for designing a filter for the chip is as

shown in the flow chart. First, the desired characteristics must

be determined based on the receive channel requirements. The

decimation rates for the CIC filters must then be selected such

that their performance is near that of the desired channel re-

quirements. Finally, an algorithm such as the Parks-McClellan

or Remez exchange is used to compute the final spectral re-

quirements, including droop correction for passband loss of the

CIC filters. If the designed filter meets the requirements, then

the filter is acceptable. If not, another combination of CIC filter

decimation must be examined. Tables III and IV greatly sim-

plify distribution and selection of CIC requirements. The

filter software available from Analog Devices helps to auto-

mate this procedure.

SELECT FILTER

REJECTION

REQUIREMENTS

DOES CIC2 FILTER

PROTECT ENOUGH

BANDWIDTH?

SELECT

DECIMATION

RATE FOR CIC5

DESIGN RCF

WITH REMEZ

EXCHANGE

YES

SELECT

DECIMATION

RATE FOR CIC2

DOES CIC5 FILTER

PROTECT ENOUGH

BANDWIDTH?

DOES COMPOSITE

FILTER PROVIDE

THE DESIRED

RESULTS?

YES

Figure 53. Diagram of Filter Design Software

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