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AD6620S/PCB 数据表(PDF) 8 Page - Analog Devices

部件名 AD6620S/PCB
功能描述  65 MSPS Digital Receive Signal Processor
PDF  43 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6620S/PCB 数据表(HTML) 8 Page - Analog Devices

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AD6620
–8–
REV. 0
SERIAL PORT: BUS MASTER
RESET with PAR/SER = “0” establishes Serial Port active.
SBM = “1” puts AD6620 in Serial Bus Master mode SCLK is
output; SDFS is output.
tSCLKD
tSCLKL
tSCLKH
CLK
SCLK
tSCLK
Figure 9. SCLK Switching Characteristics
tSSI
tHSI
DATA
SDI
SCLK
Figure 10. Serial Input Data Timing Requirements
SCLK
tDSF
tDSE
tSDFEH
tSDFSH
SDFS
SDFE
Figure 11. Serial Frame Switching Characteristics
tDSO
I15
I14
I13
SCLK
SDO
Figure 12. Serial Output Data Switching Characteristics
SERIAL PORT: CASCADE MODE
RESET with PAR/SER = “0” establishes Serial Port active.
SBM = “0” puts AD6620 in Serial Port Cascade mode, SCLK
is input; SDFS is input.
tSCLK
tSCLKH
tSCLKL
SCLK
Figure 13. SCLK Timing Requirements
tSSI
tHSI
SCLK
SDI
DATA
Figure 14. Serial Input Data Timing Requirements
SCLK
SDFS
tSSF
tHSF
Figure 15. SDFS Timing Requirements
tDSO
I15
I14
SCLK
SDO
tDSE
tSDFEH
Q1
Q0
SDFE
Figure 16. SDO, SDFE Switching Characteristics



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