AD6620SSLASHPCB datasheet(27/43 Pages) AD

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AD6620

–27–

REV. 0

If the AD6620s to be synchronized have identical decimation,

then latency through the filter stages will be matched and output

data rates for the Sync master’s filter stages will match the cor-

responding filter stages of the slave.

SYNC M/S

MASTER

SLAVE

SYNC CIC

SYNC RCF

MASTER

SLAVE

Figure 47. SYNC_CIC, SYNC_RCF Pins

The three SYNC inputs to the control block originate from the

same three bidirectional pads from which the three SYNC out-

puts are driven. When the AD6620 is a SYNC MASTER, the

internal circuitry that generates the SYNC pulse outputs is

enabled to the pads. When the AD6620 is a SYNC SLAVE, the

internally produced SYNC pulses are three-stated, and the pads

are driven from an external input. The capacitance on these pins

must be closely monitored since the master responds to the

same SYNC pulse as the slave (its own pulse). There is no input

requirement to the relative phases of these SYNC pulses. In the

absence of SYNC pulses each state machine will free run so the

latter decimation filters can be reliably synchronized by the

SYNC pulses of an earlier stage. However, when sync pulses are

provided externally, setup-and-hold times must be met for each

respective input.

CONTROL REGISTERS AND ON-CHIP RAM

The AD6620 provides a choice of two control ports. It has an 8-

bit generic microprocessor port that is used for configuring the

device at boot up and dynamically reconfiguring the AD6620 in

the system. It also has a synchronous serial port that can also

dynamically reconfigure the AD6620 for the desired system

operation. All control registers are available from both the serial

port and the microprocessor port. These control methods are

nonexclusive and the two ports can be used simultaneously. If

simultaneous access occurs, the serial port is given precedence

over the microprocessor port unless a micro cycle is already

under way. The microprocessor port deasserts the or RDY

signal and waits until the serial access is completed. Output data

is also available from the serial port; this feature is described in

detail in the Serial Port Control section. The mapping of the

AD6620 internal registers is provided below.

Table VI. Control Register and RAM Addresses

Address

Bit Width

Name

Notation

Description

000–0FF

RCF Coefficient RAM

100–1FF

RCF Data RAM

200–27F

Reserved

300

MODE CONTROL REGISTER

0: SOFT_RESET

1: Diversity Channel Real Input Mode

2: Single Channel Complex Input Mode

3: Sync Master/Slave2 (Master = 1,

Slave = 0)

7–4: Reserved

301

NCO CONTROL REGISTER

0: NCO Bypass (Bypass = 1, Active= 0)

1: Enable Phase Dither

2: Enable Amplitude Dither

7–3: Reserved

302

NCO SYNC CONTROL REGISTER

SYNC_MASK

Write: Sync Mask Shadow

Read: Sync Mask

303

NCO_FREQ

Channel Frequency for NCO Tuning

304

NCO PHASE_OFFSET

NCO Phase Offset

305

INPUT/CIC2 SCALE REGISTER

2–0: SCIC2

3: Reserved

4: ExpInv

7–5: : ExpOff

306

MCIC2 – 1

CIC2 Decimation Minus One

307

CIC5 SCALE REGISTER

SCIC5

4–0: SCIC5

7–5: Reserved

308

MCIC5 – 1

CIC5 Decimation Minus One

309

OUTPUT/RCF CONTROL REGISTER

SOUT

2–0: Output Scale Factor

7–3: Reserved

30A

MRCF – 1

RCF Decimation Minus One

30B

RCF ADDRESS OFFSET REGISTER

RCFOFF

Filter Coefficient Address Offset

30C

NTAPS – 1

Number of Taps Minus One

30D

Reserved (Should Be Written 0)

NOTES

1This bit is set high on

RESET. The chip is held into SOFT_RESET until it is written low.

2This bit is set low on

RESET. This keeps multiple AD6620 SYNC Masters from driving each other.

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