AD6620SSLASHPCB datasheet(10/43 Pages) AD

10 / 43 page

AD6620

–10–

REV. 0

MICROPORT MODE1, READ

Timing is synchronous to CLK; MODE = 1.

DATA VALID

tSC

ADDRESS VALID

N+1

N+2

N+3

CLK1

R/W2

DS2

CS3

D[7:0]

DTACK

A[2:0]

tSAM

N+4

tHC

tDD

tHC

tZD

tHA

tDTACK

NOTES:

1 DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),

CLK "N=2" OTHERWISE.

2 THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.

3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS

AND FORCE

DTACK HIGH.

tSC

tZR

Figure 19. MODE1 Read Timing Requirements and Switching Characteristics

MICROPORT MODE1, WRITE

Timing is synchronous to CLK; MODE = 1.

tSC

N+1

N+2

N+3

tSAM

tDTACK

tSC

CLK1

R/W2

DS2

CS3

D[7:0]

DTACK

A[2:0]

tHC

tDTACK

tSAM

tHM

tHA

NOTES:

1 ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.

2 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.

3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE

AND FORCE

DTACK HIGH.

* THE NEXT WRITE MAY BE INITIATED ON CLK, N*.

DATA VALID

ADDRESS VALID

Figure 20. MODE1 Write Timing Requirements and Switching Characteristics

AD6620S/PCB 数据表(PDF) 10 Page - Analog Devices

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AD6620S/PCB 数据表(PDF) 10 Page - Analog Devices

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