AD6620SSLASHPCB datasheet(26/43 Pages) AD

26 / 43 page

AD6620

–26–

REV. 0

The maximum number of taps this filter can calculate, NTAPS, is

given by the equation below. The value NTAPS minus 1 is writ-

ten to the AD6620 internal address space at address 30C hex.

The decimation ratio of this filter, MRCF, may be programmed

from 1 to 32. The input rate into the RCF is fSAMP5. NCH is equal

to two for Diversity Channel Real Input mode; otherwise NCH = 1.

TAPS

CLK

RCF

SAMPS

≤













min

, 256

The RCF coefficients are located in addresses 0x000 to 0x0FF

and are interpreted as 20-bit twos complement numbers. When

writing the coefficient RAM, the lower addresses will be multi-

plied by relatively older data from the CIC5 and the higher

coefficient addresses will be multiplied by relatively newer data

from the CIC5. The coefficients need not be symmetric and the

coefficient length, NTAPS, may be even or odd. If the coefficients

are symmetric, then both sides of the impulse response must be

written into the coefficient RAM.

The RCF stores the data from the CIC5 into a 256

× 36 RAM.

256

× 18 is assigned to I data and 25 × 18 is assigned to Q data.

The RCF uses the RAM as a circular buffer, so that it is difficult

to know in which address a particular data element is stored. To

avoid start-up transients due to undefined data RAM values, the

data RAM should be cleared upon initialization. The RCF

utilizes the number of data RAM locations equal to NTAPS × NCH,

rounded up to the nearest even number, starting from address

0x100, so these are the only values that need be cleared.

When the RCF is triggered to calculate a filter output, it starts

by multiplying the oldest value in the data RAM by the first

coefficient (located by the RCFOFF register in address 0x30B).

This value is accumulated with the products of newer data words

multiplied by the subsequent locations in the coefficient RAM

until the coefficient address RCFOFF + NTAPS–1 is reached.

Table V. Three-Tap Filter

Coefficient Address

Impulse Response

Data

h(0)

n(0) Newest

h(1)

n(1)

2 (NTAPS – 1)

h(2)

n(2) Oldest

The output rate of this filter is determined by the output rate of

the CIC5 stage and MRCF.

SAMPR

SAMP

RCF

RCF Coefficient Address Offset

This register at address 30C hex allows the AD6620 to place

multiple filters in the RAM. However, the sum of the taps re-

quired may not exceed 256 divided by the number of channels.

The RCF will compute the filter from RCF_OFFSET to

(RCF_OFFSET + NTAPS). A single access can then be used to

select which of the filters is used without requiring coefficients

be rewritten.

RCF Output Scale Factor

The scale factor associated with the RCF, SOUT, behaves differ-

ently than the scale factors in the CIC stages. This scalar, at the

RCF output, controls the weight of the 16-bit output data going

to the parallel port or to the serial port when using 16-bit words.

SOUT determines which of the 23 RCF output bits are used

based on the equation below. OLRCF is the 23-bit RCF output

data; POL represents the output port data. POL is rounded to

the 16 bits desired. The weight of the rounding is adjusted by

SOUT. When the serial port is used with 24-bit or 32-bit words,

SOUT is ignored.

POL

round OLRCF

SOUT

=×

)

( –)

216

Filter Phase Synchronization

Like the NCO, the AD6620 filter stages have phase synchroni-

zation circuitry enabling multiple AD6620s to be used in appli-

cations such as diversity antennas and phased array systems.

For any fSAMP, there are MCIC2 possible phases of fSAMP2 at the

output of the CIC2 stage. Similarly, at the output of the CIC5

stage, there are MCIC5 possible phases of fSAMP5. This means that

at the output of the CIC stages there is already MCIC2

× M

CIC5

possible phases of the filtered data. Additional phase uncertainty

is introduced by decimation done in the RCF. At the output of

the AD6620 there are a total of MCIC2

× M

CIC5

× M

RCF possible

output phases of the data.

In diversity systems using multiple AD6620s, it is necessary to

ensure that the output of each AD6620 in the system is in phase.

A variety of system issues (e.g., not bringing the AD6620s on

line at the same time, excessive digital noise) could cause the

AD6620s to start out-of-phase or to drift out-of-phase as the

system runs. To achieve output phase coherence in such sys-

tems the SYNC_CIC and SYNC_RCF pins are provided.

The function of these pins is controlled by the SYNC_M/S bit

in the Mode Control Register at address 300 hex of internal

address space. When the SYNC_M/S bit is high, SYNC_CIC

and SYNC_RCF provide synchronization pulses on the rising

edge of CLK. When the SYNC_M/S bit is low, SYNC_CIC and

SYNC_RCF accept external synchronization pulses sampled on

the rising edge of clock. This pulse edge synchronizes the CIC2,

CIC5 and RCF filter stages of all AD6620 in the chain.

Below is an example of the output SYNC pulse waveforms.

The SYNC_NCO pulse is not shown and is described in the

preceding NCO Synchronization section. Each SYNC_RCF

output pulse is concurrent with a SYNC_CIC pulse. The

SYNC_RCF output pulse can be connected to the SYNC_CIC,

and SYNC_RCF inputs of another AD6620 to achieve full

decimation synchronization.

CLK

SYNC CIC

SYNC RCF

Figure 46. SYNC Output Pulses

In the example above, MCIC2 = 2, and MCIC5 = 2 as evidenced

by the SYNC_CIC pulses that occur every 4 CLK cycles

(MCIC2

× M

CIC5). MRCF = 3, resulting in SYNC_RCF pulses

that are one third as frequent as the SYNC_CIC pulses. In this

example full rate input timing is employed such that the input

data rate equals the clock rate.

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