AD6620SSLASHPCB datasheet(19/43 Pages) AD

19 / 43 page

AD6620

–19–

REV. 0

A/BOUT

IF DVOUT is low, A/BOUT is always low. When A/BOUT is high,

A Channel data is available on the output. If DVOUT remains

high while A/BOUT is low, then B Channel data is on the output

pins of the chip OUT[15:0].

CLK

OUT[15:0]

VALID DATA

A DATA

tDPR

tDPF

DVOUT

I/QOUT

A/BOUT

Figure 33. Parallel Output Data Timing (Single-Channel

Mode)

tDPR

tDPF

VALID DATA

A DATA

B DATA

CLK

OUT[15:0]

DVOUT

I/QOUT

A/BOUT

Figure 34. Parallel Output Data Timing (Diversity Channel

Mode)

Serial Output Data Port

The AD6620 provides a choice of two output ports: a 16-bit

parallel port and a synchronous serial port. The advantage of

using the serial port is that all 23 bits of available data can be

output in the 24-bit or 32-bit mode. The serial output port

shares some of the same pins used by the parallel output port.

As a result, one or the other mode of output may be utilized,

but not both. The output mode must be set with a hard reset

generated by at least a 30 ns low time on the

RESET pin. If the

PAR/SER line is low (logic “0”) upon reset, then serial output

data is activated. The PAR/SER pin should remain static after

the output mode has been set (i.e., PAR/SER should only change

when

RESET is low).

Note that the AD6620 cannot be booted through the serial port.

The microport must be used to initialize the device, then serial

operation is supported.

Figure 35 shows the typical interconnections between an AD6620

in serial master mode and a DSP. Refer to the Serial Control

Port section for a detailed description of pin functions and pro-

cedures for writing and reading with relation to the serial port.

Note the 10 k

Ω resistors connected to SDI and SDO. These

prevent the lines from toggling when the AD6620 or DSP

three-states these pins.

SCLK

AD6620

DSP

+3.3V

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

Figure 35. Typical Serial Data Output Interface to DSP

(Serial Master Mode, SBM = 1)

Figure 36 shows two AD6620s illustrating the cascade capability

for the chip. The first is connected as a serial master and the

second is configured in serial cascade mode. The SDFE signal

of the master is connected to the SDFS of the slave. This allows

the master AD6620 data to be obtained first by the DSP, fol-

lowed by the cascade AD6620 data.

SCLK

AD6620

DSP

+3.3V

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

10k

SCLK

AD6620

CASCADE

SBM

SDI

SDO

SDFS

SDFE

SDIV

Figure 36. Typical Serial Data Output Interface to DSP

(Serial Cascade Mode, SBM = 0)

AD6620S/PCB 数据表(PDF) 19 Page - Analog Devices

AD6620S/PCB 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表下载

链接网址

AD6620S/PCB 数据表(PDF) 19 Page - Analog Devices

AD6620S/PCB 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表 下载

链接网址

数据表下载