AD6620SSLASHPCB datasheet(28/43 Pages) AD

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AD6620

–28–

REV. 0

(0x000–0xFF) RCF COEFFICIENT RAM

Memory that stores user-programmable coefficients for the RCF

filter. The RAM will hold 256 20-bit twos complement words

for a maximum filter length of 256 taps. In Diversity Channel

Real Mode the filter length is limited to 128 taps per channel.

The number of taps used is controlled by NTAPS–1 (30C) re-

gardless of the number of coefficient locations programmed. If

filter size allows, more than one filter can be resident in the

memory at a time. This makes it possible to switch filters with-

out reloading all of the coefficients.

(0x100–0x1FF) RCF DATA RAM

These locations store I and Q data exiting the CIC5 filter stage

while the RCF performs multiply accumulates. The lower 18

bits of the 36-bit location is I data; the upper 18 bits are Q data.

These locations are addressed in memory and are available via

the control ports so that the data RAM can be flushed for test-

ing and simulation purposes. They are not cleared on reset.

(0x300) MODE CONTROL REGISTER

This location brings the chip out of reset and sets the operating

mode. It also specifies how the chip will use its SYNC pins: as

outputs while acting as a sync master, or as inputs while acting

as a sync slave. This is the only register with a defined power-up

state: on power-up, Bit 0 will be at a Logic “1.” This places the

chip in SOFT_RESET and defines the chip as a sync slave.

Powering up as a sync slave avoids contention problems when

connecting multiple AD6620s.

If Bit 0 is written low and Bits 2 and 1 are low, the AD6620 is in

Single Channel Real Mode. If Bit 1 is high and Bits 0 and 2 are

low, the device is in the Diversity Channel Real Mode. If Bit 2 is

high and Bits 0 and 1 are low, the chip is in the Single Channel

Complex Mode. Setting Bit 3 high configures the AD6620 as a

SYNC master; the SYNC pins are then used as outputs. If Bit 3

is low, it is a SYNC slave and the SYNC pins function as inputs.

Bits 7–4 are reserved and should be written low.

(0x301) NCO CONTROL REGISTER

This register allows control of special features of the NCO. If

Bit 0 of this register is high the NCO of the AD6620 is by-

passed. Both the I data and the Q data that are passed through

the chip will be the same and the Spectrum will not be trans-

lated. In bypass the input data is attenuated by 12 dB.

The NCO has two features to improve the performance of some

systems: Phase Dither and Amplitude Dither. These can be

used together or alone. If Bit 1 of the register is high, Phase

Dither is activated. If Bit 2 is high, Amplitude Dither is acti-

vated. For more information on dither refer to the NCO section.

(0x302) NCO SYNC CONTROL REGISTER

This holds the SYNC_MASK, which controls the frequency of

the SYNC_NCO pulses and therefore the phase accuracy of the

synchronization. See the NCO section for details.

(0x303) NCO_FREQ

This register holds the NCO frequency control word as de-

scribed in the NCO section. This is a 32-bit unsigned integer

that sets the frequency of the AD6620 NCO.

(0x304) NCO PHASE_OFFSET

This register controls the phase offset of the NCO. It is also

described in detail in the NCO section and can be used to allow

for phase differences between multiple antennas receiving the

same carrier.

(0x305) INPUT/CIC2 SCALE REGISTER

This register holds the scale factor, SCIC2, for CIC2. SCIC2 scales

down the data before it is accumulated in CIC2. This avoids

eliminates the resulting spectral errors. SCIC2 is contained in Bits

2–0 of this register. It is treated as an unsigned integer between

0 and 6. Increasing SCIC2 shifts data down. For more details

refer to the section on the CIC2 filter.

The second function of this register is to scale the input data

from the Parallel Data Input port. This allows the AD6620 to

treat the floating point input data with considerable flexibility.

There are two parts of this function. The first is Bit 4, which

tells the AD6620 how to handle the exponent, EXP[2:0]. If this

bit is low, data is shifted down as the exponent increases. If this

bit is high, then for increasing EXP[2:0] the input data is shifted

up. The second part of the input data shifting is the Exponent

Offset(ExpOff[7 . . 5]) held in Bits 7–5 of this register. This

provides gain to the input data as described in the Input Port

section.

(0x306) (MCIC2 – 1)

This register controls the amount of decimation in the CIC2

filter stage. The value contained in this register is the CIC2

decimation rate minus one. This is interpreted as an unsigned

8-bit integer but due to limited growth in the CIC2 filter accu-

mulators this value should be limited to 15 (decimation = 16).

(0x307) SCIC5

This register holds the scale factor, SCIC5, for CIC5. SCIC5 scales

down the data before it is accumulated in CIC5. This avoids

eliminates the resulting spectral errors. SCIC5 is contained in Bits

4–0 of this register. It is treated as an unsigned integer between

0 and 20. Increasing SCIC5 shifts data down. For more details

refer to the section on the CIC5 filter.

(0x308) (MCIC5 – 1)

This register controls the amount of decimation in the CIC5

filter stage. The value contained in this register is the CIC5

decimation rate minus one. This is interpreted as an unsigned

8-bit integer, but due to limited growth in the CIC5 filter accu-

mulators this value should be limited to 31 (decimation = 32).

(0x309) OUTPUT/RCF CONTROL REGISTER

Bits 2-0 of this register hold the Output Scale Factor, SOUT.

These bits are interpreted as a 3-bit unsigned integer, the value

of which controls which of the 23 output bits of the RCF are

passed to the output port being used. The data output corre-

sponds to the following equation where OLRCF is the 23-bit

output of the RCF and POL is the 16-bit data available at the

parallel output port or the serial port when 16-bit serial words

are used. The truncation function rounds the scaled 23-bit

number to 16 bits. SOUT is ignored when WL is 24 or 32 bits. In

most applications, this register should be set to 4 as an initial

starting value.

POL

OLRCF

OUT

=×

()

( –)

Bits 7–3 of this register are reserved and must be written 0.

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