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AD6620

–17–

REV. 0

Diversity Channel Real Mode

In the Diversity Channel Real mode the A/B pin serves not only

as an input enable but also to determine which channel is being

sampled on a given CLK edge. A high on the A/B pin marks

channel A data and a low on A/B marks channel B data. The

AD6620 only accepts the first sample after an A/B transition.

All subsequent samples are disregarded until A/B changes again.

When full rate input timing is employed in the Diversity Chan-

nel Real mode, A/B must toggle on every edge of CLK for new

data to be clocked into the AD6620.

tSI

tHI

CLK

IN[15:0]

EXP[2:0]

A/B

BN+1

AN+1

AN+2

BN+2

Figure 30. Full Rate Input Timing, Diversity Channel Real

Mode

If fractional rate input timing is necessary in the Diversity Chan-

nel Real Mode, the A/B pin must toggle at half the rate of the

A/D sample clock. The timing diagram below shows a 3

× pro-

cessing clock. In this situation there will be one ADC encode

pulse for every three AD6620 CLK pulses and data must be

taken on every third CLK pulse. The CLK edges that corre-

spond to the latching of A and B channel data are shown in

Figure 31.

tSI

tHI

CLK

IN[15:0]

EXP[2:0]

A/B

Figure 31. Fractional Rate Input Timing (3

× CLK), Diversity

Channel Real Mode

Single Channel Complex Mode

In the Single Channel Complex input mode, A/B high identi-

fies the in-phase samples and A/B low identifies quadrature

samples. The quadrature samples are paired with the previous

in-phase samples. The timing for this mode is the same as that

of the Diversity Channel Real Mode. This mode is useful for

accepting complex output data from another AD6620 or an-

other source to increase filtering and or decimation rates.

In the Single Channel Complex Mode the CIC2 decimation

must be set to two (MCIC2 = 2). This is necessary in order to

allow enough CLK cycles to process the complex input data as

described below.

First clock cycle: (A/B high).

– I data loaded from the input port.

– The I data-path gets I

× cosine.

– The Q data-path gets I

× sine.

– The first integrator of the CIC2 adds these values to its

previous sums.

– The rest of the CIC2 is idle.

Second clock cycle: (A/B low).

– Q data loaded from the input port.

– The I data-path gets Q

× sine.

– The Q data-path gets Q

× cosine.

– The first integrator of the I path of the CIC2 completes the

sum (I

× cosine - Q × sine) and the first integrator of the Q

path of the CIC2 completes the sum j(I

× sine + Q × cosine).

– The rest of the CIC2 operates on these sums, which is the

complete complex multiply. The data is then multiplexed

through the rest of the chip as if it were single channel real data.

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