AD6620SSLASHPCB datasheet(20/43 Pages) AD

20 / 43 page

AD6620

–20–

REV. 0

The AD6620 also supports a serial slave mode, where the serial

clock and interface is provided by a DSP or ASIC that is set to

operate in the master mode. Note that the AD6620 cannot be

booted through the serial port. The microport must be used to

initialize the device, then serial operation is supported.

In the serial slave mode, DVOUT is valid and indicates the pres-

ence of a new word in the output buffers of the shift register.

This pin may thus be used by the DSP to generate an interrupt

to service the serial port. The DSP then generates an SFDS

pulse to drive the AD6620. The first serial clock rising edge

after SDFS makes the first bit available at SDO. The falling

edge of serial clock can be used to sample the data. The total

number of bits are then read from the AD6620 (determined by

the serial port word length). If the DSP has the ability to count

bits, the DSP will know when the complete frame is read. If not,

the DSP can monitor the SDFE pin to determine that the com-

plete frame is read.

The serial clock provided by the DSP can be asynchronous with

the AD6620 clock and input data. The only constraint is that

the clock be fast enough to read the serial frame prior to the

next frame coming available. Since the AD6620 output is syn-

chronous with its input sample rate the output update rate can

be determined by the user-programmed decimation rate. The

timing diagram in Figure 38 details how serial slave mode is

implemented.

SCLK

AD6620

DSP

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

DVOUT

IRQ

Figure 37. Typical Serial Data Output Interface to DSP

(Serial Slave Mode, SBM = 0)

tDSO

DVOUT

SCLK

SDFS

SDO

DSP USES FALLING EDGE OF

DVOUT TO GENERATE SDFS

FIRST DATA IS AVAILABLE THE FIRST

RISING SCLK AFTER SDFS GOES HIGH

IMSB

IMSB – 1

DVOUT PULSEWIDTH IS 2 CLKIN

SINGLE CHANNEL AND 4 CLKIN

DUAL CHANNEL

Figure 38. Timing for Serial Slave Mode (SBM = 0)

FREQUENCY TRANSLATOR

The first signal processing stage is a frequency translator con-

sisting of two multipliers and a 32-bit complex numerically

controlled oscillator (NCO). The NCO serves as a quadrature

local oscillator capable of producing any analytic frequency

between –fSAMP/2 and +fSAMP/2 with a resolution of fSAMP/2

32. In

the Single Channel Real input mode, fSAMP is equal to fCLK

multiplied by the fraction of CLK cycles that A/B is high. In the

Diversity Channel Real and Single Channel Complex input

modes, fSAMP is equal to fCLK multiplied by the fraction of CLK

cycles on which A/B has been toggled. The NCO worst case

discrete spur is better than –100 dBc for all output frequencies.

The control word, NCO_FREQ is interpreted as a 32-bit un-

signed integer. To translate a channel centered at fCH to dc,

calculate NCO_FREQ using the equation below. The mod

function is used here to allow for Super Nyquist sampling where

the IF carrier(fCH) is larger than the sample rate(fSAMP). The

mod removes the integer portion of the number and forces it

into the 32-bit NCO Frequency Register. If the fraction re-

maining is larger than 0.5, the NCO will be tuning above the

Nyquist rate. The corresponding signal is then aliased back into

the first Nyquist Zone as a negative frequency.

NCO FREQ

SAMP

mod

=×

232

In both Single and Diversity Channel Real Input modes, the

output of the translation stage is the complex product of the real

input samples and the complex samples from the NCO. It is

necessary for the subsequent decimating filters to reject the

unwanted image of the channel of interest, as well as any un-

wanted neighboring signals (and their images) not rejected by

previous analog filters.

In the Diversity Channel Real Input mode, the same NCO

output words are used for both channel A and B streams, result-

ing in identical phase shifts. In Single Channel Complex mode

both I and Q inputs are multiplied by the quadrature outputs of

the NCO. The I and Q products of the multiply are then pro-

cessed in the AD6620 filter stages.

Phase Dither

The AD6620 provides a phase dither option for improving the

spurious performance of the NCO. This is controlled via the

NCO Control Register at address 301 hex. When phase dither is

enabled by setting Bit 1 of this register high, spurs due to phase

truncation in the NCO are randomized. The energy from these

spurs is spread into the noise floor and Spurious Free Dynamic

Range is increase at the expense of very slight decreases in the

SNR. Phase dither should be experimented with for each de-

sired NCO frequency and if it is seen to reduce spurs, it should

be considered. The choice of whether Phase Dither is used in a

system will ultimately be decided by the system goals. If lower

spurs are desired at the expense of a slightly raised noise floor, it

should be employed. If a low noise floor is desired and the higher

spurs can be tolerated or filtered by subsequent stages, then

Phase Dither is not needed.

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