AD6620SSLASHPCB datasheet(16/43 Pages) AD

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AD6620

–16–

REV. 0

The Exponent Offset is used to shift the data right. For ex-

ample, Table I shows that with no ExpOff shift, 12 dB of range

is lost when the ADC input is at the largest level. This is undes-

ired because it lowers the Dynamic Range and SNR of the sys-

tem by reducing the signal of interest relative to the quantization

noise floor.

To avoid this automatic attenuation of the full-scale ADC sig-

nal, the Exponent Offset is used to move the largest signal (RSSI =

5) up to the point where there is no downshift. In other words,

once the Exponent Invert bit has been set, the Exponent Offset

should be adjusted so that mod(7–5 + ExpOff,8) = 0. This is

the case when Exponent Offset is set to 6 since mod(8, 8) = 0.

Table II illustrates the use of ExpInv and ExpOff when used

with the AD6600 ADC.

Table II. AD6600 Transfer Function with AD6620 ExpInv = 1,

and ExpOff = 6

ADC Input

Data

Signal

Level

RSSI[2.0]

Division

Reduction

Largest

101 (5)

/ 32 (<< 0)

–0 dB

100 (4)

/ 16 (<< 1)

–6 dB

011 (3)

/ 8 (<< 2)

–12 dB

010 (2)

/ 4 (<< 3)

–18 dB

001 (1)

/ 2 (<< 4)

–24 dB

Smallest

000 (0)

1 (<< 5)

–30 dB

(ExpInv = 1, ExpOff = 6)

This flexibility in handling the exponent allows the AD6620 to

interface with other gain ranging ADCs besides the AD6600.

The Exponent Offset can be adjusted to allow up to seven

RSSI(EXP) ranges to be used as opposed to the AD6600s five.

It also allows the AD6620 to be tailored in a system that employs

the AD6600, but does not utilize all of its signal range. For

example, if only the first four RSSI ranges are expected to occur

then the Exponent Offset could be adjusted to five, which would

then make RSSI = 4 correspond to the 0 dB point of the AD6620.

IN4

IN3

IN2

IN1

IN0

EXP2

EXP1

EXP0

IN15

D10 (MSB)

D0 (LSB)

AD6600

AD6620

A/B

RSS12

RSS11

RSS10

A/B OUT

Figure 27. Typical Interconnection of the AD6600 Gain-

Ranging ADC and the AD6620 in a Diversity Application

Input Timing

The CLK signal is used to sample the input port and clock the

synchronous signal processing stages that follow. The CLK signal

can operate up to 65 MHz and have a duty cycle of 45% to

55%. In applications using high speed ADCs, the ADC sample

clock is typically used to clock the AD6620. Applications that

require a faster signal processing clock than the ADC sample

clock, may employ fractional rate input timing as shown in the

following sections. The input timing requirements vary accord-

ing to the mode of operation. Fractional rate input timing cre-

ates a longer “don’t care” time for the input data so that slower

ADCs need only meet the setup-and-hold conditions for their

data with respect to their own sample clock cycle, rather than

the faster signal processing clock. The ADC sample clock may

be any integer fraction of CLK up to and including 1, as long as

the clock and data rate are less than or equal to 65 MSPS.

Single Channel Real Mode

In the Single Channel Real mode the A/B input pin functions as

an active high input enable. If the A/D sample clock is fast enough

to perform the necessary filter functions, full rate input timing

can be used and A/B should be tied high as shown in Figure 28.

N+1

N+2

N+3

N+4

tSI

tHI

CLK

IN[15:0]

EXP[2:0]

A/B

Figure 28. Full Rate Input Timing, Single Channel

Real Mode

When a faster processing clock is used to achieve better filter

performance, the A/D data must be synchronized with the faster

AD6620 CLK signal. This is achieved by having the ADC clock

rate an integer fraction of the AD6620 clock rate. AD6620 input

data is sampled at the slower ADC clock rate. In the Single

Channel Real Mode this is achieved by dynamically controlling

the A/B input and bringing it high before each CLK edge that

data is to be sampled on. A/B must be returned low before the

next high speed clock pulse and the duty cycle of the A/B signal

will therefore be equal to the data-to-clock ratio.

N+1

tSI

tHI

CLK

IN[15:0]

EXP[2:0]

A/B

Figure 29. Fractional Rate Input Timing (4

× CLK), Single

Channel Real Mode

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