S12OSCV2D datasheet(67/126 Pages) FREESCALE

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MC9S12DJ64 Device User Guide — V01.17

Section 4 Modes of Operation

4.1 Overview

Eight possible modes determine the operating configuration of the MC9S12DJ64. Each mode has an

associated default memory map and external bus configuration.

Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during

reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating

mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA

pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting

of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the

memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin

is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.

For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide.

Table 4-1 Mode Selection

BKGD =

MODC

PE6 =

MODB

PE5 =

MODA

PK7 =

ROMCTL

ROMON

Bit

Mode Description

000

Special Single Chip, BDM allowed and ACTIVE. BDM is

allowed in all other modes but a serial command is

required to make BDM active.

001

Emulation Expanded Narrow, BDM allowed

Special Test (Expanded Wide), BDM allowed

011

Emulation Expanded Wide, BDM allowed

Normal Single Chip, BDM allowed

101

Normal Expanded Narrow, BDM allowed

110

Peripheral; BDM allowed but bus operations would cause

bus conﬂicts (must not be used)

111

Normal Expanded Wide, BDM allowed

Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS

Description

Colpitts Oscillator selected

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