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S12OSCV2D 数据表(PDF) 88 Page - Freescale Semiconductor, Inc |
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S12OSCV2D 数据表(HTML) 88 Page - Freescale Semiconductor, Inc |
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88 / 126 page  MC9S12DJ64 Device User Guide — V01.17 88 A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. Table A-2 ESD and Latch-up Test Conditions Model Description Symbol Value Unit Human Body Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Number of Pulse per pin positive negative - - 1 1 Machine Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Number of Pulse per pin positive negative - - 3 3 Latch-up Minimum input voltage limit -2.5 V Maximum input voltage limit 7.5 V Table A-3 ESD and Latch-Up Protection Characteristics Num C Rating Symbol Min Max Unit 1 T Human Body Model (HBM) VHBM 2000 - V 2 T Machine Model (MM) VMM 200 - V 3 T Charge Device Model (CDM) VCDM 500 - V 4T Latch-up Current at TA = 125°C positive negative ILAT +100 -100 -mA 5T Latch-up Current at TA = 27°C positive negative ILAT +200 -200 -mA |
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