| 数据搜索系统,热门电子元器件搜索 |
|
S12OSCV2D 数据表(PDF) 97 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
S12OSCV2D 数据表(HTML) 97 Page - Freescale Semiconductor, Inc |
|
97 / 126 page ![]() MC9S12DJ64 Device User Guide — V01.17 97 A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. The Integral Non-Linearity (INL) is defined as the sum of all DNLs: Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz Num C Rating Symbol Min Typ Max Unit 1 P 10-Bit Resolution LSB 5 mV 2 P 10-Bit Differential Nonlinearity DNL –1 1 Counts 3 P 10-Bit Integral Nonlinearity INL –2.5 ±1.5 2.5 Counts 4P 10-Bit Absolute Error1 NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter. AE -3 ±2.0 3 Counts 5 P 8-Bit Resolution LSB 20 mV 6 P 8-Bit Differential Nonlinearity DNL –0.5 0.5 Counts 7 P 8-Bit Integral Nonlinearity INL –1.0 ±0.5 1.0 Counts 8P 8-Bit Absolute Error1 AE -1.5 ±1.0 1.5 Counts DNL i () V i V i1 – – 1LSB ------------------------ 1 – = INL n () DNL i () i1 = n ∑ V n V 0 – 1LSB -------------------- n – == |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |