S12OSCV2D datasheet(71/126 Pages) FREESCALE

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MC9S12DJ64 Device User Guide — V01.17

Section 5 Resets and Interrupts

5.1 Overview

Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and

interrupts.

5.2 Vectors

5.2.1 Vector Table

Table 5-1 lists interrupt sources and vectors in default order of priority.

Table 5-1 Interrupt Vector Locations

Vector Address

Interrupt Source

CCR

Mask

Local Enable

HPRIO Value

to Elevate

$FFFE, $FFFF

Reset

None

–

$FFFC, $FFFD

Clock Monitor fail reset

None

PLLCTL (CME, SCME)

–

$FFFA, $FFFB

COP failure reset

None

COP rate select

–

$FFF8, $FFF9

Unimplemented instruction trap

None

–

$FFF6, $FFF7

SWI

None

–

$FFF4, $FFF5

XIRQ

X-Bit

None

–

$FFF2, $FFF3

IRQ

I-Bit

IRQCR (IRQEN)

$F2

$FFF0, $FFF1

Real Time Interrupt

I-Bit

CRGINT (RTIE)

$F0

$FFEE, $FFEF

Enhanced Capture Timer channel 0

I-Bit

TIE (C0I)

$EE

$FFEC, $FFED

Enhanced Capture Timer channel 1

I-Bit

TIE (C1I)

$EC

$FFEA, $FFEB

Enhanced Capture Timer channel 2

I-Bit

TIE (C2I)

$EA

$FFE8, $FFE9

Enhanced Capture Timer channel 3

I-Bit

TIE (C3I)

$E8

$FFE6, $FFE7

Enhanced Capture Timer channel 4

I-Bit

TIE (C4I)

$E6

$FFE4, $FFE5

Enhanced Capture Timer channel 5

I-Bit

TIE (C5I)

$E4

$FFE2, $FFE3

Enhanced Capture Timer channel 6

I-Bit

TIE (C6I)

$E2

$FFE0, $FFE1

Enhanced Capture Timer channel 7

I-Bit

TIE (C7I)

$E0

$FFDE, $FFDF

Enhanced Capture Timer overﬂow

I-Bit

TSRC2 (TOI)

$DE

$FFDC, $FFDD

Pulse accumulator A overﬂow

I-Bit

PACTL (PAOVI)

$DC

$FFDA, $FFDB

Pulse accumulator input edge

I-Bit

PACTL (PAI)

$DA

$FFD8, $FFD9

SPI0

I-Bit

SPICR1 (SPIE, SPTIE)

$D8

$FFD6, $FFD7

SCI0

I-Bit

SCICR2

(TIE, TCIE, RIE, ILIE)

$D6

$FFD4, $FFD5

SCI1

I-Bit

SCICR2

(TIE, TCIE, RIE, ILIE)

$D4

$FFD2, $FFD3

ATD0

I-Bit

ATDCTL2 (ASCIE)

$D2

$FFD0, $FFD1

ATD1

I-Bit

ATDCTL2 (ASCIE)

$D0

$FFCE, $FFCF

Port J

I-Bit

PIEJ

(PIEJ7, PIEJ6, PIEJ1, PIEJ0)

$CE

$FFCC, $FFCD

Port H

I-Bit

PIEH (PIEH7-0)

$CC

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