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STM8S103F2 数据表(PDF) 72 Page - STMicroelectronics |
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STM8S103F2 数据表(HTML) 72 Page - STMicroelectronics |
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72 / 117 page  Unit Max Typ Min Conditions Parameter Symbol Load = 20 pF 50 (3) - - Standard and high sink I/Os Load = 20 pF μA ±1 (2) - - VSS ≤ VIN ≤VDD Digital input leakage current Ilkg nA ±250 (2) - - VSS ≤ VIN ≤ VDD Analog input leakage current Ilkg ana μA ±1 (2) - - Injection current ±4 mA Leakage current in adjacent I/O Ilkg(inj) (1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. (2)Data based on characterisation results, not tested in production. (3)Data guaranteed by design. Figure 22: Typical VIL and VIH vs VDD @ 4 temperatures DocID15441 Rev 9 72/117 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics |
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