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STM8S103F2 数据表(PDF) 17 Page - STMicroelectronics |
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STM8S103F2 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 117 page ![]() • Analog watchdog capability with programmable upper and lower thresholds • Analog watchdog interrupt • External trigger input • Trigger from TIM1 TRGO • End of conversion (EOC) interrupt Communication interfaces 4.14 The following communication interfaces are implemented: • UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, single wire mode, LIN2.1 master capability • SPI : Full and half-duplex, 8 Mbit/s • I²C: Up to 400 Kbit/s UART1 4.14.1 Main features • One Mbit/s full duplex SCI • SPI emulation • High precision baud rate generator • Smartcard emulation • IrDA SIR encoder decoder • LIN master mode • Single wire half duplex mode Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency • Separate enable bits for transmitter and receiver • Two receiver wakeup modes: - Address bit (MSB) - Idle line (interrupt) • Transmission error detection with interrupt generation • Parity control Synchronous communication • Full duplex synchronous transfers • SPI master operation • 8-bit data communication • Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16) 17/117 DocID15441 Rev 9 Product overview STM8S103K3 STM8S103F3 STM8S103F2 |
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