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STM8S103F2 数据表(PDF) 40 Page - STMicroelectronics |
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STM8S103F2 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 117 page  Reset status Register name Register label Block Address Reserved area (1008 bytes) 0x00 5410 to 0x00 57FF (1)Depends on the previous reset source. (2)Write only register. CPU/SWIM/debug module/interrupt controller registers 6.2.3 Table 9: CPU/SWIM/debug module/interrupt controller registers Reset status Register name Register label Block Address 0x00 Accumulator A CPU (1) 0x00 7F00 0x00 Program counter extended PCE 0x00 7F01 0x00 Program counter high PCH 0x00 7F02 0x00 Program counter low PCL 0x00 7F03 0x00 X index register high XH 0x00 7F04 0x00 X index register low XL 0x00 7F05 0x00 Y index register high YH 0x00 7F06 0x00 Y index register low YL 0x00 7F07 0x03 Stack pointer high SPH 0x00 7F08 0xFF Stack pointer low SPL 0x00 7F09 0x28 Condition code register CCR 0x00 7F0A Reserved area (85 bytes) 0x00 7F0B to 0x00 7F5F 0x00 Global configuration register CFG_GCR CPU 0x00 7F60 0xFF Interrupt software priority register 1 ITC_SPR1 ITC 0x00 7F70 0xFF Interrupt software priority register 2 ITC_SPR2 0x00 7F71 0xFF Interrupt software priority register 3 ITC_SPR3 0x00 7F72 0xFF Interrupt software priority register 4 ITC_SPR4 0x00 7F73 0xFF Interrupt software priority register 5 ITC_SPR5 0x00 7F74 DocID15441 Rev 9 40/117 STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map |
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