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STM8S103F2 数据表(PDF) 35 Page - STMicroelectronics |
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STM8S103F2 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 117 page  Reset status Register name Register label Block Address Reserved area (21 bytes) 0x00 523B to 0x00 523F 0x00 TIM1 control register 1 TIM1_CR1 TIM1 0x00 5250 0x00 TIM1 control register 2 TIM1_CR2 0x00 5251 0x00 TIM1 slave mode control register TIM1_SMCR 0x00 5252 0x00 TIM1 external trigger register TIM1_ETR 0x00 5253 0x00 TIM1 interrupt enable register TIM1_IER 0x00 5254 0x00 TIM1 status register 1 TIM1_SR1 0x00 5255 0x00 TIM1 status register 2 TIM1_SR2 0x00 5256 0x00 TIM1 event generation register TIM1_EGR 0x00 5257 0x00 TIM1 capture/compare mode register 1 TIM1_CCMR1 0x00 5258 0x00 TIM1 capture/compare mode register 2 TIM1_CCMR2 0x00 5259 0x00 TIM1 capture/compare mode register 3 TIM1_CCMR3 0x00 525A 0x00 TIM1 capture/compare mode register 4 TIM1_CCMR4 0x00 525B 0x00 TIM1 capture/compare enable register 1 TIM1_CCER1 0x00 525C 0x00 TIM1 capture/compare enable register 2 TIM1_CCER2 0x00 525D 0x00 TIM1 counter high TIM1_CNTRH 0x00 525E 35/117 DocID15441 Rev 9 Memory and register map STM8S103K3 STM8S103F3 STM8S103F2 |
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