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STM8S103F2 数据表(PDF) 18 Page - STMicroelectronics |
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STM8S103F2 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 117 page  LIN master mode • Emission: Generates 13-bit synch break frame • Reception: Detects 11-bit break frame SPI 4.14.2 • Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave • Full duplex synchronous transfers • Simplex synchronous transfers on two lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • CRC calculation • 1 byte Tx and Rx buffer • Slave/master selection input pin I²C 4.14.3 • I²C master features: - Clock generation - Start and stop generation • I²C slave features: - Programmable I2C address detection - Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • Supports different communication speeds: - Standard speed (up to 100 kHz) - Fast speed (up to 400 kHz) DocID15441 Rev 9 18/117 STM8S103K3 STM8S103F3 STM8S103F2 Product overview |
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