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STM32F217VG 数据表(PDF) 75 Page - STMicroelectronics |
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STM32F217VG 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 175 page ![]() DocID17050 Rev 9 75/175 STM32F21xxx Electrical characteristics 174 Typical and maximum current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog inputs by firmware. • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to 30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz and 3 wait states from 90 to 120 MHz). • When the peripherals are enabled HCLK is the system clock, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2, except is explicitly mentioned. • The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Table 19. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM (1) Symbol Parameter Conditions fHCLK Typ Max(2) Unit TA = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Run mode External clock(3), all peripherals enabled(4) 120 MHz 49 63 72 mA 90 MHz 38 51 61 60 MHz 26 39 49 30 MHz 14 27 37 25 MHz 11 24 34 16 MHz(5) 821 30 8 MHz 5 17 27 4 MHz 3 16 26 2 MHz 2 15 25 External clock(3), all peripherals disabled 120 MHz 21 34 44 90 MHz 17 30 40 60 MHz 12 25 35 30 MHz 7 20 30 25 MHz 5 18 28 16 MHz(5) 4.0 17.0 27.0 8 MHz 2.5 15.5 25.5 4 MHz 2.0 14.7 24.8 2 MHz 1.6 14.5 24.6 1. Code and data processing running from SRAM1 using boot pins. 2. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 3. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 4. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. In this case HCLK = system clock/2. |
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